1. Field of the Invention
The present invention relates to a semiconductor device (a semiconductor memory device) having a function of a memory. The present invention relates to a method for operating the semiconductor device.
2. Description of the Related Art
As processing of an LSI (Large Scale Integrated Circuit) becomes complicated, capacitance of a memory device (a memory) which is inside of an LSI has been increased. In particular, capacitance of a cache memory or the like which is incorporated into a CPU (Central Processing Unit) is greatly increased. A cache memory is a memory for storing frequently-used data in order to accelerate processing speed, and necessary capacitance of the cache memory becomes large as processing capability of a CPU is improved. Accordingly, the ratio whose a cache memory takes up in the whole area of an LSI becomes greatly high. Since the cache memory has a large area, influence on yield of a chip in the whole LSI, power consumption, and the like has also been increased.
FIG. 5 shows a conventional memory cell. An inverter loop 108 includes two N-channel transistors 111 and 113, and two P-channel transistors 112 and 114. An input terminal 104 of the memory cell is a power supply line, and an input terminal 105 is a ground line. A power voltage is supplied to the memory cell thorugh the power supply line and the ground line.
Gate terminals of N-channel transistors 106 and 107 are connected to an input terminal 103 of the memory cell. Drain terminals of the N-channel transistors 106 and 107 are connected to input terminals 101 and 102 of the memory cell respectively. Source terminals of the N-channel transistors 106 and 107 are connected to nodes 109 and 110 of the inverter loop 108 respectively.
In the case of writing a value (also referred to as data) into the memory cell in FIG. 5, the input terminal 103 which is a word line for writing is held at a HIGH state to turn on the N-channel transistors 106 and 107. At this time, a value to be written is held in the input terminal 101, and an inverted value of which is written is held in the input terminal 102, so that the value is written into the memory cell.
When a value is read from the memory cell in FIG. 5, the input terminal 103 is held at a HIGH state to turn on the N-channel transistors 106 and 107. At this time, the input terminals 101 and 102 are held at a potential between a HIGH state and a LOW state (hereinafter described as an intermediate potential) to read the value from the memory cell, and the potential difference is amplified in a reading circuit so that the value is read.
A memory cell which employs six transistors can form an SRAM (Static Random Access Memory). In the case of manufacturing an SRAM in this manner, it is necessary that a value of the memory cell is not rewritten by a current from the input terminals 101 and 102. Specifically, when the N-channel transistors 106 and 107 are turned on at the time of reading, it is necessary that a value of the memory cell is not rewritten by a current from the input terminals 101 and 102 which are held at intermediate potentials.
However, if variation in the threshold voltage or the like of transistors is large, a value of the memory cell is rewritten at the time of reading. An RF circuit is sensitive to the threshold voltage of the transistor, and in particular, a malfunction due to variation in the threshold voltage of the transistors is generated in the case of employing thin film transistors as the transistors.
Description will be made below of the case where a value of the memory cell is rewritten at the time of reading when variation in the threshold voltage of the transistors is large with reference to FIG. 5, using a power supply voltage of 5 V.
The input terminals 101 and 102 are held at the intermediate potentials at the time of reading. A potential in the inverter loop 108 is determined by a current flowing into the memory cell through the N-channel transistors 106 and 107 which are turned on and a current supplied from the transistors which are in the inverter loop 108 in the memory cell.
When variation in the threshold voltage of these transistors is within the scope of the assumption at the time of designing, miswriting of a value of the memory cell does not occur at the time of reading. Description will be made of the case where, for example, the threshold voltage of the N-channel transistor 113 is relatively high, and the threshold voltage of the P-channel transistor 112 is relatively low. In addition, the N-channel transistors 106 and 107 are turned on, that is, the input terminals are turned on when the node 109 is held at 5 V and the node 110 is held at 0 V.
When the N-channel transistors 106 and 107 are turned on, a current flows from the input terminal 101 into the memory cell through the N-channel transistor 106. At this time, the potential of the node 109 becomes lower than the power supply voltage of 5 V and a little bit higher than the intermediate potential of 2.5 V for an instance by a current flowing from the power supply to the node 109 through the P-channel transistor 112 which is turned on. Accordingly, the voltage of the node 110 which is an output of an inverter formed of the N-channel transistor 113 and the P-channel transistor 114 becomes higher than 0 V.
At this time, since the threshold voltage of the N-channel transistor 113 is high and the value of a current which flows to the N-channel transistor 113 at the potential a little bit higher than the intermediate potential decreases, a current from the P-channel transistor 114 increases so that the voltage of the node 110 is rewritten to be 5 V.
As described above, when the characteristic variation in the transistors is large, a configuration of six transistors as shown in FIG. 5 is not suitable for an SRAM. Therefore, a port for writing and a port for reading are separated from each other so that a wrong value cannot be written at the time of reading. For example, by employing a configuration which is disclosed in Reference 1 (Reference 1: Japanese Published Patent Application No. 08-161890) where a port for writing and a port for reading are separated from each other, a wrong value cannot be written at the time of reading. Note that the configuration where a port for writing and a port for reading are separated from each other can achieve, high integration of the memory cell, which is an object of Reference 1.
By separating a port for writing and a port for reading from each other with the configuration of the memory cell which is disclosed in Reference 1, there is no possibility that miswriting occurs at the time of reading. However, in the case of employing this configuration of the memory cell, a complicated circuit such as a precharge circuit is necessary for a reading circuit. It is to be noted that a precharge circuit is provided in a reading circuit and holds a data line for reading at a HIGH state in a period other than a reading period.